// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// Generated by Quartus II 64-Bit Version 13.0 (Build Build 232 06/12/2013)
// Created on Sat Apr 23 00:17:02 2016

bus bus_inst
(
	.ava_wr_n(ava_wr_n_sig) ,	// input  ava_wr_n_sig
	.ava_rd_n(ava_rd_n_sig) ,	// input  ava_rd_n_sig
	.ava_addr(ava_addr_sig) ,	// input [15:0] ava_addr_sig
	.ava_data_out(ava_data_out_sig) ,	// input [15:0] ava_data_out_sig
	.ava_data_in(ava_data_in_sig) ,	// output [15:0] ava_data_in_sig
	.wr_n(wr_n_sig) ,	// output  wr_n_sig
	.rd_n(rd_n_sig) ,	// output  rd_n_sig
	.addr(addr_sig) ,	// output [15:0] addr_sig
	.data_out(data_out_sig) ,	// output [15:0] data_out_sig
	.data_in(data_in_sig) 	// input [15:0] data_in_sig
);

